High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
A dynamic random access memory (DRAM), which is a typical semiconductor memory device, stores information by charges accumulated in cell capacitors, and, therefore, the information is lost unless refresh operations are periodically carried out. Therefore, refresh commands indicating refresh operations are periodically issued from a control device, which controls a DRAM. The refresh commands are issued from the control device at a frequency that all the word lines are certainly refreshed one time in the period of 1 refresh cycle (for example, 64 msec). In addition, the refresh command is periodically stolen as Row-Hammer refresh (RHR) which maintains data retention of a row-address of a victim caused by Row-Hammer attack.
However, a conventional static Row-Hammer refresh rate control may not prevent bit errors due to Row Hammer effects that may occur at various timings from various causes and dynamic Row Hammer refresh rate control may be desired.